Technology

ViArrays – Analog/Mixed-Signal Circuit IP

ViArrays are composed of several configurable primitive resources (transistors, resistors, capacitors, diodes, etc.). These resources are sized and grouped in the ViArray forming an analog/mixed-signal fabric for implementation of IP blocks (e.g., amplifiers, comparators, analog/digital filters, ADC’s, DAC’s, PLL’s, DC-DC converters, linear regulators). The table below lists some examples of circuit IP that has been developed on ViArrays.
Circuits IP Examples

Specifications
Data Converters
Sigma Delta ADC
24bit, 19.8 ENOB, 20sps, DNL 1LSB, PSRR 45dB, Gain Error +/-0.2%

Pipelined, Flash ADC
100MSPS, 12bit
Power Management
PWM, Current, R2R DACs
4-20 bits: 20bit, 4mA output, DNL 8LSB, PSRR 45dB, Gain Error 1.5%

DC – DC Converters
Buck, Boost, Buck-Boost, 1.2V to 100V, 100nA to 5A
Analog
LDOs
NMOS, PMOS, 42V up to 2A

Precision References
0.1%, 5ppm/degC, 12uVpp, 120dBc THD
Digital
Charge Pumps
3V to 48V up to 1A

Amplifiers & Comparators
4ns Propagation Delay, 1 GHz+ GBW, > 18V
Timing
VCSEL & LED Drivers
50mA to 1.5A, 3V to 32V
Switched Capacitor
BW > 10 MHz, SNR > 80 dB
Signal Processing
IIR, FIR, Pulse-Shaping, Commutating Filter, Filter, CORDICs
Microprocessors
RISC V, 8051, ARM M0, Proprietary Micro/Sequencer
Comms Interface
I2C, I3C, SPI, UART, USART, CAN, LIN, USB, RS485
PLLs
1MHz to 480MHz
On-Chip Oscillators
10 kHz to 100 MHz

Radiation-Hardened &
Tolerant Integrated Solutions

Integrated solutions in aerospace and defense applications are often exposed to the transient and long-term effects of radiation. These can include single event effects (SEEs) such as single-event upsets (SEUs), single-event transients (SETs), and single-event latch-up (SELs). Long-term effects result from exposure to ionizing energy or total ionizing dose (TID), causing changes like threshold voltage shifts and mobility degradation.

Rad-Hard by Process and
Rad-Hard by Design

To mitigate radiation effects, two primary approaches are generally used: Radiation Hardening by Process (RHBP) and Radiation Hardening by Design (RHBD). The former requires a specific semiconductor process like silicon-on-insulator (SOI). The latter, RHBD, applies a specific set of electrical and layout techniques to bulk CMOS, a more widely available technology. Both RHBP and RHBD can achieve strategic levels of radiation hardness.

Radiation-Hardened
ViArray Technology and Qualification

TMD’s patented ViArray technology is applicable to both RHBP and RHBD. Regardless of the approach, TMD’s Rad-Hard ViArrays are loaded with a wide variety of analog and digital, highly configurable resources resulting in an optimal solution for radiation-hardened devices.

ViArrays can be completely configured with a single via-layer, while leaving underlying radiation-assured resources unchanged, eliminating the need for requalification.

The single mask configurability of TMD’s analog/mixed- signal fabric directly supports the “Qualification by Similarity” concept, resulting in a cost-effective solution to the qualification challenges faced by the aerospace and defense industry. All of TMD’s ViArrays are qualified to MIL-PRF-38535. This means, regardless of the design put on the ViArray, the resulting chip will still meet qualification requirements.

TMD Rad-Hard
ViArray™ Advantages

Relevant Radiation Tolerant and Hardened Mixed-Signal IP

Analog to Digital Converters
ΔΣ, SAR, Pipelined, Flash
Digital to Analog Converters
ΔΣ, R2R, Segmented, Current Steering, Switched Cap, PWM
VREF/Power Management
Bandgap/DTMOS References, Buck, Boost, & LDO Regulators
Analog/Digital Signal Processing
TIAs, LNAs, Switched Cap, PLL/DLLs, One-Bit Signal Processing, MCUs
DC to 50MSPS 4 to 20bits
Up to
100MSPS
6 to 20bits
Up to 60V
Up to 2A
AFEs with
mod/demod
Image ViArray Qualification Reports available upon request.

Triad Micro Devices Solutions for
Emerging Chiplet Applications

As chiplet technology revolutionizes the design of complex System-on-Chip (SoC) architectures, new challenges inevitably emerge. Chiplet-based designs must grapple with issues such as level shifting, protocol translation, power management, sensor interfaces, test coverage, and unanticipated bugs or late feature requests. The ViArray devices from TMD offer powerful, cost-effective solutions to these challenges.

Level Shifting and
Protocol Translation

Analog Front End
Sensor Interfaces

Level Shifting and
Protocol Translation

While the Universal Chiplet Interconnect Express (UCIe) interface is gradually gaining acceptance for intra-chiplet communication, the current reality is a more loosely defined “Bunch of Wires” (BoW) standard. Chiplets must often translate communication protocols between dies and perform voltage level translations. TMD’s ViArray devices serve as an intermediary for these crucial functions, ensuring timely and cost-effective voltage and protocol translation.

Analog Front End
Sensor Interfaces

TMD’s ViArrays offer a breakthrough for chiplet solutions. These configurable arrays can craft specialized Analog Front Ends (AFEs), catering to unique sensor needs, while ensuring a consistent digital interface. This ensures swift and seamless integration of diverse sensors into heterogeneous System-in-Package architectures.

Power Management

As chiplets combine to form a complete solution, managing power requirements becomes a complex task. Multiple voltage domains, varying current profiles, specific power up and down sequencing, and power and thermal monitoring all need to be coordinated. These requirements often emerge late in the system design process. TMD’s ViArray devices can be utilized as a Power Management IC (PMIC), providing a cost-effective and low-risk approach to chiplet system power management.

Test Coverage

The integration of chiplets also presents a challenge for test coverage. Individual chiplets can usually be directly tested when their pads are probed, but they may lack the ability for easy testing and verification within the chiplet system. TMD’s ViArray devices, with their easy configurability and mix of both analog and digital resources, can be used to create comprehensive mixed-signal scan chains. They can be combined with a chiplet to create a Built-In Self Test (BIST) feature, with the ViArray acting as an in-system test device.

Addressing the Unknowns

Chiplet systems are complex, heterogenous, and designed to address challenging real-world problems. The likelihood of encountering unknown issues during development is high, whether in the form of bugs or late feature requests. In these cases, it may be prohibitively expensive to respin a Deep Submicron (DSM) chiplet. However, ViArrays offer a timely and cost-effective means to address these challenges.